The present invention relates to a technique which is effective when applied to a semiconductor device having a structure in which inner leads among the device leads are arranged on a circuit formation face of a semiconductor chip encapsulated in a package body.
There is a package having an LOC (Lead On Chip) structure representing one of the surface mount type LSI packages. The package has a structure such that the inner leads among the device leads are arranged via a tape-shaped insulating film on the main surface of a semiconductor chip, that is, on a circuit formation face on which a plurality of semiconductor devices and bonding pads are formed, and the inner leads and the bonding pads on the semiconductor chip are electrically connected by Au wires. The insulating film has a laminated structure obtained by coating an adhesive on both faces of a base film made of a heat-resisting resin such as polyimide. A package having a LOC structure of this kind is described in, for example, Japanese Patent Application Laid-Open Nos. 61-218139, 61-236130, and the like.
On the other hand, since engineering workstations and personal computers of recent years require a memory (RAM) of large capacity in order to process a large amount of data at high speed, a technique for laminating a memory module is being examined.
As a specific example, there is a known laminated-type memory module in which a plurality of thin LSI packages, such as TSOPs (Thin Small Outline Packages) and TSOJs (Thin Small Outline J-lead Packages), are piled up, and outer leads of the upper and lower packages are connected by soldering or the like and are fixed on a printed wiring board. For example, a technique is described in Japanese Patent Application Laid-Open No. 5-175406 whereby outer leads of TSOJs are bent upward in the middle and a part of each of the outer leads is extended in the horizontal direction, thereby overlapping the leads of the upper and lower packages.